1. Field of the Invention
The present invention relates to a differential amplifier circuit, and particularly to a differential amplifier circuit for amplifying the potential difference between an input signal and a reference signal to output a complementary two-phase signal.
2. Description of the Prior Art
Since the GaAs semiconductor has an electron mobility several times faster than Si and allows a semi-insulating substrate to easily be obtained, it is assumed that the parasitic capacity of the circuit can be reduced in the integration process to allow a high-speed logical operation, and thus, based on such assumption, various efforts are moving toward the practical utilization of an optical communication system using such GaAs circuit which has an operation speed of 10 Gbps or higher. Further, the development of 20 to 40 Gbps Ics is proceeded while terabit transmission is taken into consideration.
Specifically, in a high-speed optical communication system of 10 Gbps or higher, the variable-gain amplifier connected to the rear stage of a preamplifier is difficult to speed up as compared with the preamplifier, and thus, as a countermeasure against this, a circuit construction is considered in which the variable-gain amplifier is operated by two-phase driving with the output of the preamplifier being a complementary output. As such circuit, a GaAs source-coupled logic circuit (hereinafter described as SCFL circuit) as shown in FIG. 11, which can easily provide a complementary output, is suitable.
As shown in FIG. 11, the SCFL circuit has a construction in which one end of a resistor 1 used as a load is connected to a power supply terminal 100, the other end of the resistor 1 is connected to an output terminal 41, one end of a resistor 2 is connected to the power supply terminal 100, the other end of the resistor 2 is connected to an output terminal 42, the drain electrode of a field effect transistor (hereinafter described as FET) 11 is connected to the output terminal 41, the gate electrode of the FET 11 is connected to an input terminal 51, the source electrode of the FET 11 is connected to a node 61, the drain electrode of an FET 12 is connected to the output terminal 42, the gate electrode of the FET 12 is connected to an input terminal 52, the source electrode of the FET 12 is connected to the node 61, the drain electrode of an FET 13 is connected to the node 61, the gate electrode of the FET 13 is connected to a control terminal 43, and the source electrode of the FET 13 is connected to a power supply terminal 101.
Now, if one input terminal 51 is applied with a sufficiently high voltage relative to the input terminal 52, a current flows through the FET 11 and the FET 12 cuts off, and thus, the potential at the output terminal 41 drops, while the potential at the output terminal 42 rises.
On the other hand, when a low voltage is applied to the input terminal 51, the FET 11 cuts off and a current flows through the FET 12, and thus the potential at the output terminal 41 rises and the potential at the output terminal 42 drops, resulting in a complementary output.
Generally, the potential at either input terminal is given as a reference potential, and the differential voltage between this potential and the input signal potential is amplified. To form a preamplifier using such circuit, the circuit must be constructed so that it can cover a photodetector current variation in response to the intensity of an optical signal, and the reference potential must be given to it from the outside, or must be internally generated.
Conventionally, as this countermeasure, a technique using current mirror shown in Japanese Patent Application Laid-Open No. 8-195719 has been employed. In this circuit, as shown in FIG. 12, by amplifying the current of a photodetector 204 in a second preamplifier 203 by the use of a current mirror circuit 202, an offset compensation is made so that the average value of the input signal becomes a reference potential.
In the circuit of FIG. 12, the output of the photodetector 204 is input to one input terminal of a differential amplifier circuit 200 through a first preamplifier 201, while the current mirror circuit 202 is connected to the photodetector circuit 204 and the output of the current mirror circuit is input to the other input terminal of the differential amplifier circuit 200 via the second preamplifier 203. This means that a signal based on a current of the same value as the average current flowing through the photodetector is input to the other input terminal of the differential amplifier circuit, by which the offset voltage at the output of the differential amplifier circuit is eliminated to make an offset compensation.
However, this circuit has a problem that the power consumption of the circuit increases, because the second preamplifier is required for the offset compensation. Further, if a reference signal is used, there is a problem that the voltage gain becomes half as compared with the case in which the differential amplifier circuit is driven by a two-phase signal.
It is the object of the present invention to provide a differential amplifier circuit in which a two-phase signal can be obtained from a single-phase signal, the increases in the number of elements and in the power consumption can be suppressed, and a high voltage gain and a wide dynamic range can be provided.